Register Memory Organization in PIC 16F877

To read the previous articles on the basics of PIC 16F877, click on the links below.

TAKE A LOOK : PERIPHERAL INTERFACE CONTROLLER (PIC)

TAKE A LOOK : INTRODUCTION TO PIC 167F877

TAKE A LOOK : PIC 16F877 – ARCHITECTURE AND MEMORY ORGANIZATION

Register Memory Organization in PIC 16F877

A register is a place inside the PIC which used to read or write the data/program. The memory of the PIC is divided into a series of registers. Each of the registers has its own address and memory locations. These addresses are normally denoted by using hexadecimal numbers. According to the type of working and usage, the registers in PIC are classified into two categories.

General Purpose Registers (GPR)

GPR is a small amount of storage that can be accessible more quickly than any other memory. These register files can be accessed either directly, or indirectly, through the File Select Register (FSR). The General Purpose Register (GPR) memory map (PIC16F877A) is shown in the figure below.

Special Function Registers (SFR)

The special function registers are also memory registers which is used for special dedicated functions. These registers perform various dedicated functions inside the PIC chip. Each special function inside this PIC chip is controlled by using these registers. These registers are used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are normally implemented as in the form of static RAM memory. A list of these registers is given in the tables below. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. The figures below shows SFR memory map of PIC16F877.

Status Register

Status register is an eight bit register that contains the arithmetic status of the arithmetic logic unit (ALU), the reset status and the bank select bits for the data memory. The detailed explanation of status register is given below.

Status registers (address 03h, 83h, 103h, and 183h)

R/W*-0	R/W-0	R/W-0	R-1	R-1	R/W-x**	R/W-x	R/W-x
IRP	RP1	RP0	TO	PD	Z	DC	C

Bit7                                                                                                                                                                                           Bit 0

(*R/W-readable/writable, **x-unknown bit)

• Bit 7 – (IRP): this is a Register Bank Select Bit usually used for indirect addressing mode.
• Bit 6-5 (RP1:RP0): these bits are Register Bank Select bits commonly used for direct addressing mode (each banks in this mode carry 128 byes)

(11 = Bank 3 (180h-1FFh)

10 = Bank 2 (100h-17Fh)

01 = Bank 1 (80h-FFh)

00 = Bank 0 (00h-7Fh))

• Bit 4, (TO): this is a time-out bit used for timing and counting, sleep and reset functions.

(1 = after power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred)

• Bit 3, (PD): Power-down bit

(1 = after power-up or by the CLRWDT instruction

0 = by execution of the SLEEP instruction)

• Bit 2, (Z): Zero bit

(1 = the result of an arithmetic or logic operation is zero

0 = the result of an arithmetic or logic operation is not zero.)

• Bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(For borrow, the polarity is reversed)

(1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result.)

• Bit 0 (C): Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred.)

Option Register

The option Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the pre-scaler), the external INT interrupt andTMR0 and the weak pull-ups on PORTB. Structure of option register is shown below.

R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
RBPU(inverting)	INTEDG	T0CS	T0SE	PSA	PS2	PS1	PS0

7                                                                                                                                                                                                           0

• Bit 7 (RBPU): This is a PORTB Pull-up Enable bit. If this bit is  ‘1’  then PORTB pull-up function disabled. If this bit is ‘0’, it enabled the pull-up function by individual port-latch values.

(1 = PORTB pull-ups are disabled.

0 = PORTB pull-ups are enabled by individual port latch values.)

• Bit 6 (INTEDG): This is an Interrupt Edge Select bit. This bit decided if the interrupt is on either raisin edge or falling edge. The function of this bit is given below.

(1 = Interrupt on rising edge of RB0/INT pin.

0 = Interrupt on falling edge of RB0/INT pin.)

• Bit 5 (T0CS): this is a timer-0(TMR0) Clock Source Select bit and its function is given below.

(1 = Transition on RA4/T0CKI pin.

0 = Internal instruction cycle clock (CLKO).)

• Bit 4 (T0SE): TMR0 Source Edge Select bit which select the timer 0 source edge.

(1 = Increment on high-to-low transition on RA4/T0CKI pin.

0 = Increment on low-to-high transition on RA4/T0CKI pin.)

• Bit 3 (PSA): Prescaler Assignment bit.

(1 = Prescaler is assigned to the Watch Dog Timer (WDT).

0 = Prescaler is assigned to the Timer0 module.)

• Bit 2-0 (PS2:PS0): Prescaler Rate Select bits.

INTCON Register

The INTCON register is a readable and writable register, which contains various enable and flag bits for the

TMR0 register overflow, RB port change and external RB0/INT pin interrupts. The architecture of this register is given below.

R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-x
GIE	PEIE	TMR0IE	INTE	RBIE	TMR0IF	INTF	RBIF

• Bit 7 GIE: Global Interrupt Enable bit. If this bit is enable (‘1’), which also enable all unmasked interrupts and if it is zero (‘0’), which disable all interrupts.

(1 = Enables all unmasked interrupts.

0 = Disables all interrupts.)

• Bit 6 (PEIE): this is a Peripheral Interrupt Enable bit which used for controlling peripheral interrupts. If this bit is enable(‘1’), also enable all unmasked peripheral interrupts and if it is disable(‘0’), also disable all active peripheral interrupt actions.

(1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts)

• Bit 5 (TMR0IE): This is timer 0(TMR0) Overflow Interrupt Enable bit which control the overflow interrupt in timer 0.

(1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt)

• Bit 4 (INTE): This is an RB0/INT External Interrupt Enable bit which used for enable/disable external interrupts.

(1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt)

• Bit 3 (RBIE): RB Port Change Interrupt Enable bit which control PORTB change interrupt.

(1 = Enables the RB port change interrupt.

0 = Disables the RB port change interrupt.)

• Bit 2 (TMR0IF): TMR0 Overflow Interrupt Flag bit which controls the overflow of timer 0.

(1 = TMR0 register has overflowed [must be cleared in software]

0 = TMR0 register did not overflow)

• Bit 1 (INTF): RB0/INT External Interrupt Flag control bit.

(1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur).

• Bit 0 (RBIF): RB Port Change Interrupt Flag bit.

(1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set that bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared

[Must be cleared in software] ).

PIE1 Register

The PIE1 register contains the individual enable bits for the peripheral interrupts. The structure of this register is shown below.

R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
PSPIE	ADIE	RCIE	TXIE	SSPIE	CCP1IE	TMR2IE	TMR1IE

• Bit 7 (PSPIE): this bit is the Parallel Slave Port Read/Write Interrupt Enable bit

(1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt)

• Bit 6 (ADIE): A/D Converter Interrupt Enable bit which control the analog to digital converter interrupt.

(1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt)

• Bit 5 (RCIE): USART Receive Interrupt Enable bit which control the USART data reception interrupt.

(1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt)

• Bit 4 (TXIE): USART Transmit Interrupt Enable bit that control USART data transmission.

(1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt)

• Bit 3 (SSPIE): Synchronous Serial Port Interrupt Enable bit that control SSP data interrupt.

(1 = Enables the SSP interrupt

0 = Disables the SSP interrupt)

• Bit 2 (CCP1IE): CCP1 Interrupt Enable bit which control the capture-compare-pulse width modulation interrupt.

(1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt)

• Bit 1 (TMR2IE): TMR2 to PR2 Match Interrupt Enable bit.

(1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt)

• Bit 0 (TMR1IE): TMR1 Overflow Interrupt Enable bit that control the overflow interrupt of timer 1 module.

(1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt)

PIR1 Register

The PIR1 register contains the individual flag bits for the peripheral interrupt. The structure of PIR1 register is given below.

R/W-0	R/W-0	R-0	R-0	R/W-0	R/W-0	R/W-0	R/W-0
PSPIF	ADIF	RCIF	TXIF	SSPIF	CCP1IF	TMR2IF	TMR1IF

• Bit 7 (PSPIF): Parallel Slave Port Read/Write Interrupt Flag bit.

(1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred)

• Bit 6 (ADIF): A/D Converter Interrupt Flag bit that control the interrupt flag for that analog to digital converter.

(1 = An A/D conversion completed

0 = The A/D conversion is not complete)

• Bit 5 (RCIF): USART Receive Interrupt Flag bit.

(1 = The USART receive buffer is full

0 = The USART receive buffer is empty)

• Bit 4 (TXIF): USART Transmit Interrupt Flag bit.

(1 = The USART transmit buffer is empty

0 = The USART transmit buffer is full)

• Bit 3 (SSPIF): Synchronous Serial Port (SSP) Interrupt Flag bit that control the SSP interrupt flag in a PIC.

(1 = The SSP interrupt condition has occurred and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are:

• SPI – A transmission/reception has taken place.

• I2C Slave – A transmission/reception has taken place.

• I2C Master

– A transmission/reception has taken place.

– The initiated Start condition was completed by the SSP module.

– The initiated Stop condition was completed by the SSP module.

– The initiated Restart condition was completed by the SSP module.

– The initiated Acknowledge condition was completed by the SSP module.

– A Start condition occurred while the SSP module was Idle (multi-master system).

– A Stop condition occurred while the SSP module was Idle (multi-master system).

0 = No SSP interrupt condition has occurred)

• Bit 2 (CCP1IF): CCP1 Interrupt Flag bit that control capture-compare-pulse width modulation interrupt flag. It works in three modes. They are given below.

1.      Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

2.      Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

3.      PWM mode:

• Bit 1 (TMR2IF): TMR2 to PR2 Match Interrupt Flag bit

(1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred)

• Bit 0 (TMR1IF): TMR1 Overflow Interrupt Flag bit.

(1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow)

PIE2 Register

The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision

Interrupt, EEPROM write operation interrupt and the comparator interrupt. The structure of this register is given below.

U-0	R/W-0	U-0	R/W-0	R/W-0	U-0	U-0	R/W-0
—————	CMIE	—————	EEIE	BCLIE	—————-	—————	CCP2IE

• Bit 7 Unimplemented: Read as ‘0’
• Bit 6 (CMIE): Comparator Interrupt Enable bit

(1 = Enables the comparator interrupt

0 = Disable the comparator interrupt)

• Bit 5 Unimplemented: Read as ‘0’

Bit 4 (EEIE): EEPROM Write Operation Interrupt Enable bit

(1 = Enable EEPROM write interrupt

0 = Disable EEPROM write interrupt)

• Bit 3 (BCLIE): Bus Collision Interrupt Enable bit.

(1 = Enable bus collision interrupt

0 = Disable bus collision interrupt)

• Bit 2-1 Unimplemented: Read as ‘0’
• Bit 0 (CCP2IE): CCP2 Interrupt Enable bit.

(1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt)

PIR2 Register

The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt. The structure of this register is given below.

U-0	R/W-0	U-0	R/W-0	R/W-0	U-0	U-0	R/W-0
—————	CMIF	—————	EEIF	BCLIF	————-	—————	CCP2IF

• Bit 7 Unimplemented: Read as ‘0’
• Bit 6 (CMIF): Comparator Interrupt Flag bit

(1 = the comparator input has changed (must be cleared in software)

0 = the comparator input has not changed)

• Bit 5 Unimplemented: Read as ‘0’
• Bit 4 (EEIF): EEPROM Write Operation Interrupt Flag bit.

(1 = the write operation completed (must be cleared in software)

0 = the write operation is not complete or has not been started)

• Bit 3 (BCLIF): Bus Collision Interrupt Flag bit.

(1 = A bus collision has occurred in the SSP when configured for I2C Master Mode

0 = No bus collision has occurred)

• Bit 2-1 Unimplemented: Read as ‘0’
• Bit 0 (CCP2IF): CCP2 Interrupt Flag bit. This also works in three modes. They ere

1.      Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

2.      PWM mode:

This mode is not used.

PCON Register

The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset

(POR), a Brown-out Reset (BOR),  a Watchdog Reset (WDT) and an external MCLR Reset. The structure of this register is given below.

U-0	U-0	U-0	U-0	U-0	U-0	R/W-0	R/W-1
——	——-	——-	——-	——-	———	POR(inverting)	BOR(inverting)

• Bit 7-2 Unimplemented: Read as ‘0’
• Bit 1 (POR): Power-on Reset Status bit

(1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

• Bit 0(BOR): Brown-out Reset Status bit

(1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs).